Design Decisions for Tiled Architecture Memory Systems

Tiled architectures have emerged as a solution to translate an increasing number of transistors into single application performance while keeping programming complexity under control through automatic parallelization. Tiled architectures primarily consist of an array of execution cores, interconnect networks and a memory system. Each sub-component of the tiled architecture contributes towards the overall tiled system performance, power and programmability (systemPPP). Increase in the core array size has no effect on designs of a single core and the on-chip network switch. The memory system, however, is a global subsystem, and its complexity and performance are directly influenced by the number of cores. This paper examines the scalability of existing memory system designs in the many-core regime. In this paper we discuss memory system policies for tiled architectures such as memory coherence, ordering, synchronization and caching. We also discuss the design constraints facing these memory systems including area and bandwidth. The paper then provides a summary of the memory systems of some representative tiled architectures and the mechanisms used to implement the memory system policies like load store queues. A comparative analysis and a classification is done between the important memory system mechanisms supported by these architectures. Based on the analysis, a new memory system with several mechanisms in place to help systemPPP as future work is proposed.